? semiconductor components industries, llc, 2015 january, 2015 ? rev. 6 1 publication order number: NDF08N50Z/d NDF08N50Z n-channel power mosfet 500 v, 0.85 features ? low on resistance ? low gate charge ? esd diode ? protected gate ? 100% avalanche tested ? these devices are pb ? free, halogen free/bfr free and are rohs compliant absolute maximum ratings (t c = 25 c unless otherwise noted) rating symbol NDF08N50Z unit drain ? to ? source voltage v dss 500 v continuous drain current r jc (note 1) i d 8.5 a continuous drain current r jc t a = 100 c (note 1) i d 5.4 a pulsed drain current, v gs @ 10 v i dm 34 a power dissipation p d 35 w gate ? to ? source voltage v gs 30 v single pulse avalanche energy, i d = 7.5 a e as 190 mj esd (hbm) (jesd 22 ? a114) v esd 3500 v rms isolation voltage (t = 0.3 sec., r.h. 30%, t a = 25 c) (figure 14) v iso 4500 v peak diode recovery (note 2) dv/dt 4.5 v/ns mosfet dv/dt dv/dt 60 v/ns continuous source current (body diode) i s 7.5 a maximum temperature for soldering leads t l 260 c operating junction and storage temperature range t j , t stg ? 55 to 150 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. limited by maximum junction temperature 2. i sd = 7.5 a, di/dt 100 a/ s, v dd bv dss , t j = +150 c device package shipping ordering information NDF08N50Zh to ? 220fp (pb ? free, halogen ? free) 50 units / rail n ? channel marking diagram a = location code y = year ww = work week g, h = pb ? free, halogen ? free package www. onsemi.com v dss r ds(on) (max) @ 3.6 a 500 v 0.85 NDF08N50Zg or NDF08N50Zh ayww gate source drain NDF08N50Zg to ? 220fp (pb ? free, halogen ? free) 50 units / rail NDF08N50Zg, NDF08N50Zh to ? 220fp case 221ah g (1) d (2) s (3)
NDF08N50Z www. onsemi.com 2 thermal resistance parameter symbol NDF08N50Z unit junction ? to ? case (drain) r jc 3.6 c/w junction ? to ? ambient steady state (note 3) r ja 50 3. insertion mounted electrical characteristics (t j = 25 c unless otherwise noted) characteristic test conditions symbol min typ max unit off characteristics drain ? to ? source breakdown voltage v gs = 0 v, i d = 1 ma bv dss 500 v breakdown voltage temperature co- efficient reference to 25 c, i d = 1 ma bv dss / t j 0.6 v/ c drain ? to ? source leakage current v ds = 500 v, v gs = 0 v 25 c i dss 1 a 150 c 50 gate ? to ? source forward leakage v gs = 20 v i gss 10 a on characteristics (note 4) static drain ? to ? source on ? resistance v gs = 10 v, i d = 3.6 a r ds(on) 0.69 0.85 gate threshold voltage v ds = v gs , i d = 100 a v gs(th) 3.0 3.9 4.5 v forward transconductance v ds = 15 v, i d = 3.75 a g fs 6.0 s dynamic characteristics input capacitance (note 5) v ds = 25 v, v gs = 0 v, f = 1.0 mhz c iss 730 912 1095 pf output capacitance (note 5) c oss 95 120 140 reverse transfer capacitance (note 5) c rss 15 27 35 total gate charge (note 5) v dd = 250 v, i d = 7.5 a, v gs = 10 v q g 16 31 46 nc gate ? to ? source charge (note 5) q gs 3 6.2 9 gate ? to ? drain (?miller?) charge (note 5) q gd 8 17 25 plateau voltage v gp 6.3 v gate resistance r g 3.0 resistive switching characteristics turn ? on delay time v dd = 250 v, i d = 7.5 a, v gs = 10 v, r g = 5 t d(on) 13 ns rise time t r 23 turn ? off delay time t d(off) 31 fall time t f 29 source ? drain diode characteristics (t c = 25 c unless otherwise noted) diode forward voltage i s = 7.5 a, v gs = 0 v v sd 1.6 v reverse recovery time v gs = 0 v, v dd = 30 v i s = 7.5 a, di/dt = 100 a/ s t rr 295 ns reverse recovery charge q rr 1.85 c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. pulse width 380 s, duty cycle 2%. 5. guaranteed by design.
NDF08N50Z www. onsemi.com 3 typical characteristics 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 0.0 5.0 10.0 15.0 20.0 25.0 v ds , drain ? to ? source voltage (v) i d , drain current (a) figure 1. on ? region characteristics 7.0 v v gs = 10 v 6.5 v 6.0 v 5.5 v 5.0 v 8.0 v 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 345678910 v gs , gate ? to ? source voltage (v) i d , drain current (a) figure 2. transfer characteristics v ds = 25 v t j = 150 c t j = ? 55 c t j = 25 c 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10 v gs , gate ? to ? source voltage (v) r ds(on) , drain ? to ? source resistance ( ) figure 3. on ? region versus gate ? to ? source voltage i d = 3.6 a t j = 25 c 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 t j = 25 c i d , drain current (a) figure 4. on ? resistance versus drain current and gate voltage r ds(on) , drain ? to ? source resistance ( ) v gs = 10 v 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 ? 50 ? 25 0 25 50 75 100 125 150 r ds(on) , drain ? to ? source resistance (normalized) i d = 3.6 a v gs = 10 v t j , junction temperature ( c) figure 5. on ? resistance variation with temperature 0.90 0.95 1.00 1.05 1.10 1.15 ? 50 ? 25 0 25 50 75 100 125 150 t j , junction temperature ( c) figure 6. bv dss variation with temperature bv dss , normalized breakdown voltage (v) i d = 1 ma
NDF08N50Z www. onsemi.com 4 typical characteristics 0.10 1.0 10 0 50 100 150 200 250 300 350 400 450 500 v ds , drain ? to ? source voltage (v) i dss , leakage ( a) figure 7. drain ? to ? source leakage current versus voltage t j = 150 c t j = 125 c 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 5 10 15 20 25 30 35 40 45 50 v ds , drain ? to ? source voltage (v) c, capacitance (pf) figure 8. capacitance variation t j = 25 c v gs = 0 v f = 1 mhz 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 0 4 8 121620242832 0 50 100 150 200 250 300 q g , total gate charge (nc) figure 9. gate ? to ? source voltage and drain ? to ? source voltage versus total charge v gs , gate ? to ? source voltage (v) v ds , drain ? to ? source voltage (v) q t q gd q gs v ds = 250 v i d = 7.5 a t j = 25 c v ds v gs 1.0 10 100 1000 1 10 100 r g , gate resistance ( ) t, time (ns) figure 10. resistive switching time variation versus gate resistance v dd = 250 v i d = 7.5 a v gs = 10 v t d(off) t f t r t d(on) 0.1 1.0 10.0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 125 c t j = 150 c 25 c ? 55 c v sd , source ? to ? drain voltage (v) figure 11. diode forward voltage versus current i s , source current (a) c iss c oss c rss
NDF08N50Z www. onsemi.com 5 typical characteristics v ds , drain ? to ? source voltage (v) i d , drain current (a) figure 12. maximum rated forward biased safe operating area NDF08N50Z v gs 30 v single pulse t c = 25 c 10 s 100 s 10 ms dc 1 ms r ds(on) limit thermal limit package limit 0.01 0.1 1 10 100 0.1 1 10 100 1000 pulse time (s) 50% (duty cycle) 20% 10% 5.0% 2.0% 1.0% single pulse r(t) (c/w) figure 13. thermal impedance (junction ? to ? case) for NDF08N50Z r jc = 3.6 c/w steady state 0.01 0.1 1 10 0.000001 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 leads heatsink 0.110 min measurement made between leads and heatsink with all leads shorted together. figure 14. isolation test diagram *for additional mounting information, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
NDF08N50Z www. onsemi.com 6 package dimensions to ? 220 fullpack, 3 ? lead case 221ah issue f dim min max millimeters d 14.70 15.30 e 9.70 10.30 a 4.30 4.70 b 0.54 0.84 p 3.00 3.40 e l1 --- 2.80 c 0.49 0.79 l 12.50 14.73 b2 1.10 1.40 q 2.80 3.20 a2 2.50 2.90 a1 2.50 2.90 h1 6.60 7.10 e q l1 b2 e d l p 123 b seating plane a a1 h1 a2 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. contour uncontrolled in this area. 4. dimensions d and e do not include mold flash and gate protrusions. mold flash and gate protrusions not to exceed 0.13 per side. these dimensions are to be measured at outermost extreme of the plastic body. 5. dimension b2 does not include dambar protrusion. lead width including protrusion shall not exceed 2.00. 6. contours and features of the molded package body may vary within the envelop defined by dimensions a1 and h1 for manufacturing purposes. 2.54 bsc m 0.14 m a a b c e/2 m 0.25 m a b 3x c 3x b note 3 front view side view section d ? d alternate construction section a ? a a note 6 a dd note 6 h1 on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warrant y, representation or guarantee regarding the suitability of it s products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 pubnumber/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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